fpga.cpp

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/*
 *  SatNOGS-COMMS control library
 *
 *  Copyright (C) 2024, Libre Space Foundation <http://libre.space>
 *
 *  This program is free software: you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation, either version 3 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 *  SPDX-License-Identifier: GNU General Public License v3.0 or later
 */
 
#include <etl/array.h>
#include <satnogs-comms-lib/board.hpp>
#include <satnogs-comms-lib/exception.hpp>
#include <satnogs-comms-lib/fpga.hpp>
#include <satnogs-comms-lib/power.hpp>
 
namespace satnogs::comms::lib
{

fpga::fpga(hw h, bsp::spi &spi, power &pwr, bsp::gpio &fpga_done,
           bsp::gpio &boot_sel_1, bsp::gpio &boot_sel_0)
    : m_hw(h),
      m_spi(spi),
      m_pwr(pwr),
      m_fpga_done(fpga_done),
      m_boot_sel_1(boot_sel_1),
      m_boot_sel_0(boot_sel_0)
{
  switch (m_hw) {
  case hw::NONE:
    m_name = "N/A";
    break;
  case hw::ALINX_AC7Z020:
    m_name = "ALINX-AC7Z020";
    break;
  case hw::LIBREWAVE:
    m_name = "LIBREWAVE";
    break;
  default:
    throw inval_arg_exception(__FILE__, __LINE__);
  }
  enable(false);
  /* For now the default boot mode should be QSPI */
  m_boot_sel_1.set(true);
  m_boot_sel_0.set(false);
}

void
fpga::enable(bool en)
{
  m_pwr.enable(power::subsys::FPGA_5V, en);
}

bool
fpga::enabled() const
{
  return m_pwr.enabled(power::subsys::FPGA_5V);
}
 
void
fpga::write_reg(uint32_t reg, uint32_t val)
{
  // TODO
}
 
uint32_t
fpga::read_reg(uint32_t reg)
{
  // TODO
  return 0;
}
 
void
fpga::write_reg(reg r, uint32_t val)
{
  // TODO
}
 
uint32_t
fpga::read_reg(reg r)
{
  // TODO
  return 0;
}
 
bool
fpga::get_fpga_done() const
{
  return m_fpga_done.get();
}
 
void
fpga::set_boot_mode(boot_mode mode)
{
  switch (mode) {
  case boot_mode::JTAG:
    // 0  0
    m_boot_sel_1.set(false);
    m_boot_sel_0.set(false);
    break;
 
  case boot_mode::NAND:
    // 0  1
    m_boot_sel_1.set(false);
    m_boot_sel_0.set(true);
    break;
 
  case boot_mode::EMMC:
    // 1  1
    m_boot_sel_1.set(true);
    m_boot_sel_0.set(true);
    break;
 
  case boot_mode::QSPI:
  default:
    // 1  0
    m_boot_sel_1.set(true);
    m_boot_sel_0.set(false);
    break;
  };
}
 
fpga::boot_mode
fpga::get_boot_mode() const
{
  bool sel1 = m_boot_sel_1.get();
  bool sel0 = m_boot_sel_0.get();
 
  if (sel1 == 0) {
    if (sel0 == 0) {
      // 0  0
      return boot_mode::JTAG;
    } else {
      // 0  1
      return boot_mode::NAND;
    }
  } else {
    if (sel0 == 0) {
      // 1  0
      return boot_mode::QSPI;
    } else {
      // 1  1
      return boot_mode::EMMC;
    }
  }
}
 
} // namespace satnogs::comms::lib